The present invention relates to a calibration circuit, an on die termination device and a semiconductor memory device using the same, and more particularly, to a calibration circuit for trimming a calibration code, an on die termination device and a semiconductor memory device using the same.
Various semiconductor devices embodied by using an integrated circuit chip such as a central processing unit (CPU), a memory device and a gate array are employed in various electronic devices such as a personal computer (PC), a server and a workstation. In most cases, the semiconductor device includes a receiving circuit for receiving various signals transmitted from the outside through an input pad and an output circuit for transferring an internal signal to the outside through an output pad.
As the operating speed of an electronic device is increased, the delay time generated during a signal transmission process needs to be minimized by decreasing the swing width of a signal transferred between semiconductor devices. However, as the swing width of a signal is decreased, the influence of noise is increased and a signal reflection due to an impedance mismatch of interfaces between the semiconductor devices is increased.
The impedance mismatch is generated due to external noise, a power supply voltage variation, an operating temperature variation or a manufacturing process variation. Due to the impedance mismatch, it is difficult to transfer data at a high speed, and the data can be distorted. Therefore, when a receiving device receives the distorted output data, problems such as a setup/hold failure, an input level misjudgment or the like may occur.
Therefore, for solving the above-mentioned problems, the memory device required for a high speed operation employs an impedance matching circuit, called an on die termination, near a pad in a chip. Generally, in an on die termination scheme, a transmission device performs a source termination through an output circuit and a receiving device performs a parallel termination through a termination circuit connected in parallel to a receiving circuit coupled to the input pad.
A ZQ calibration is a process performed at a ZQ node for a calibration. The ZQ calibration process is performed for generating a pull-up calibration code (PCODE) and a pull-down calibration code (NCODE) which vary according to a PVT (Process, Voltage and Temperature) condition. By using the codes generated according to the ZQ calibration, a resistance of the on die termination device and a termination resistance of a DQ pad in case of a semiconductor memory device are adjusted.
FIG. 1 is a schematic circuit diagram showing a conventional ZQ calibration circuit included in an on die termination device or a semiconductor memory device.
As shown, the conventional ZQ calibration circuit employed in the on die termination device or the semiconductor memory device includes a pull-up calibration resistance circuit 101; a dummy calibration resistance circuit 103; a pull-down calibration resistance circuit 105; a reference voltage generator 107; a first and a second comparators 109 and 111; a pull-up counter 113; and a pull-down counter 115.
The pull-up calibration resistance circuit 101 includes a plurality of pull-up resistors which are turned on/off according to a pull-up calibration code PCODE<N:0>. The pull-up calibration resistance circuit 101 is calibrated with an external resistor 117 coupled to a ZQ node in order to generate the pull-up calibration code PCODE<N:0>.
The first comparator 109 compares a voltage of the ZQ node (VZQ) connected to the external resistor 117 coupled to a ZQ pin and the pull-up calibration resistance circuit 101 with a reference voltage VREF generated by the reference voltage generator 107 in order to generate an up/down signal UP/DOWN. Herein, a voltage level of the reference voltage VREF is generally set to VDDQ/2.
The pull-up counter 113 generates the pull-up calibration code PCODE<N:0> based on the up/down signal UP/DOWN outputted from the first comparator 109. Then, a resistance of the pull-up calibration resistance circuit 101 is adjusted by turning on/off the resistors connected in parallel included in the pull-up calibration resistance circuit 101 according to the generated pull-up calibration code PCODE<N:0>. Thereafter, the adjusted resistance of the pull-up calibration resistance circuit 101 varies a voltage VZQ of the ZQ node again.
By repeatedly performing the above-mentioned process, a whole resistance of the pull-up calibration resistance circuit 101 is equalized to a resistance of the external resistor 117, thereby completing a pull-up calibration process. Herein, the resistance of the external resistor 117 is generally 240 ohms.
A circuit structure of the dummy calibration resistance circuit 103 is same to that of the pull-up calibration resistance circuit 101. The pull-down calibration resistance circuit 105 includes a plurality of pull-down resistors which are turned on/off according to a pull-down calibration code NCODE<N:0>. The dummy calibration resistance circuit 103 and the pull-down calibration resistance circuit 105 generate the pull-down calibration code NCODE<N:0> based on the pull-up calibration code PCODE<N:0> generated by the pull-up calibration resistance circuit 101.
The pull-up calibration code PCODE<N:0> generated by the pull-up calibration process is inputted to the dummy calibration resistance circuit 103 so that the whole resistance of the dummy calibration resistance circuit 103 is determined. Therefore, the dummy calibration resistance circuit 103 has the same resistance as the pull-up calibration resistance circuit 101.
Thereafter, a pull-down calibration process is performed. In a similar way to the pull-up calibration process, the voltage level of a pull-down calibration node a (VZQ_N) is adjusted to the voltage level of the reference voltage VREF, i.e., the pull-down calibration is performed so that the whole voltage level of the pull-down calibration resistance circuit 105 is equalized to that of the dummy calibration resistance circuit 103. Herein, the ZQ node voltage VZQ can be used as an input signal of the second comparator 111 instead of the reference voltage VREF generated by the reference voltage generator 107.
According to the pull-up and pull-down calibration codes PCODE<N:0> and NCODE<N:0> generated by the above-mentioned pull-up and pull-down calibration processes, the pull-up and pull-down termination resistances are determined. Therefore, the resistance of the on die termination device or the pull-up and pull-down termination resistances of a DQ pad included in the semiconductor memory device is determined. For instance, in case of the semiconductor memory device, the pull-up and pull-down resistances of the DQ pad have the same layout as the pull-up and pull-down calibration resistance circuits 101 and 105 shown in FIG. 1.
FIG. 2 is a schematic circuit diagram depicting a conventional pull-up and pull-down termination resistance circuit.
Referring to FIG. 2, for instance, in case of the semiconductor memory device, the pull-up and pull-down termination resistance circuit provided in an output driver of the DQ pad includes a pull-up termination resistance circuit 201 and a pull-down termination resistance circuit 205 for outputting data; and first and second pre-drivers 203 and 207 respectively connected to input terminals of the pull-up termination resistance circuit 201 and the pull-down termination resistance circuit 205.
In response to an output signal of the first pre-driver 203, the pull-up termination resistance circuit 201 is turned on so that the voltage level of a DQ pin is kept as a high level. Similarly, according to an output signal of the second pre-driver 207, the pull-down termination resistance circuit 205 is turned on so that the voltage level of the DQ pin is kept as a low level. In other words, a high level data or a low level data is outputted according to the pull-up termination or the pull-down termination.
Herein, the number of turned-on resistors of the pull-up termination resistance circuit 201 and the number of turned on resistors of the pull-down termination resistance circuit 205 are respectively determined based on code values of the PCODE<N:0> and the NCODE<N:0>. That is, whether the pull-up and the pull-down termination resistance circuits 201 and 205 are turned on or not is determined according to logic states of the PCODE<N:0> and the NCODE<N:0> outputted from the first and the second pre-drivers 203 and 207, however, each individual resistor included in the pull-up and the pull-down termination resistance circuits 201 and 205 is turned on or off according to code values of the PCODE<N:0> and the NCODE<N:0>.
DQp_CTRL and DQn_CTRL respectively inputted to the first and the second pre-drivers 203 and 207 are various control signals.
FIG. 3 is a schematic circuit diagram illustrating another conventional ZQ calibration circuit included in the on die termination device or the semiconductor memory device.
Referring to FIG. 3, unlike the circuit shown in FIG. 1, a reference voltage generator 307 generates a first reference voltage VREF+a and a second reference voltage VREF−a having a predetermined error tolerance from a reference voltage VREF. Further, first to fourth comparators 309_1, 309_2, 311_1 and 311_2; and first and second hold logic circuits 317 and 319 are included.
The first and the second comparators 309_1 and 309_2 of a pull-up calibration resistance circuit 101 compare the voltage level of a ZQ node (VZQ) with the first and the second reference voltages VREF+a and VREF−a. When outputs of the first and the second comparators 309_1 and 309_2 are different from each other, the voltage level of the ZQ node voltage VZQ is between the first and the second reference voltages VREF+a and VREF−a. At this time, the first hold logic circuit 317, for instance, generates a high-enabled hold signal P_HOLD in order to fix the PCODE by disabling a first counter 313.
The voltage gap between the first and the second reference voltages VREF+a and VREF−a is called a target range. Meanwhile, when the outputs of the first and the second comparators 309_1 and 309_2 are equal, the ZQ node voltage VZQ is higher than the first reference voltage VREF+a or lower than the second reference voltage VREF−a. In this case, the first hold logic circuit 317 inactivates the hold signal P_HOLD and transfers one of output signals (P_CNT) of the first and the second comparators 309_1 and 309_2. Then, the first counter 313 generates the PCODE based on the output signal P_CNT outputted from the first hold logic circuit 317.
A dummy calibration resistance circuit 103 and a pull-down calibration resistance circuit 105 perform the calibration operation in a similar way to the above-mentioned processes shown in FIG. 1.
Herein, the constructions 311_1, 311_2, 319 and 315 for the pull-down calibration shown in FIG. 3 can be replaced with the constructions 111 and 115 for the pull-down calibration shown in FIG. 1. In this case, the ZQ node voltage VZQ instead of the reference voltage VREF can be used as an input signal of the comparator 111.
FIG. 4 is a timing diagram illustrating an operation of the conventional calibration circuit, for instance, shown in FIG. 3. Referring to FIG. 4, for instance, when the value of PCODE<4:0> is increased gradationally during the pull-up calibration process, the resistance of the pull-up calibration resistance circuit 101 is increased gradationally so that the ZQ node voltage VZQ is gradationally decreased. As a result, when the ZQ node voltage VZQ enters the target range, the pull-up calibration process is completed.
At the following pull-down calibration process, when the value of NCODE<4:0> is decreased gradationally, the resistance of the pull-down calibration resistance circuit 105 is gradationally increased so that the pull-down calibration node voltage VZQ_N is gradationally increased. Therefore, the pull-down calibration is performed so that the pull-down calibration node voltage VZQ_N is equalized to the ZQ node voltage VZQ, i.e., the whole resistance of the pull-down calibration resistance circuit 105 is equalized to the whole resistance of the dummy calibration resistance circuit 103.
However, according to the conventional technology, although the calibration resistance and the termination resistance can be determined through the above-mentioned calibration process, an impedance mismatch may occur due to external environmental causes such as process and layout. In this case, the calibration resistance and the termination resistance need to be readjusted.